1. Technical Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection devices for integrated circuits (ICs), and, in particular, to ESD protection circuits adaptable for a microcircuit positioned in a portable data carrier.
2. Description of Related Art
As ICs have increased in integration to include larger number of circuit elements, the geometry of the circuit elements has decreased in order to maintain the overall size of the IC relatively small. With decreasing geometries of the circuit elements, providing adequate levels of ESD protection has become increasingly difficult. In Metal Oxide Semiconductor (MOS) circuits the gate oxide thickness has decreased to below around 800-1000 nanometers (nm), and breakdown voltages are often less than 10 volts.
The basic principle of operation of an ESD protection device or circuit consists in limiting to an established maximum tolerable value, dictated by a particular fabrication process, voltage spikes which may occur on the pins of integrated structures which are connected to the respective pins. As can be appreciated by those skilled in the art, the highly integrated structures are often unable to withstand voltage spikes greater than certain amplitudes.
Various ESD protection circuits have been known for some time. For example, in U.S. Pat. No. 5,600,525, Avery discloses separate protection circuits for power supply pins and input/output pins. These circuits include a plurality of silicon controlled rectifiers (SCRs) electrically connected in series. In U.S. Pat. No. 5,510,947, Pellegrini et al. disclose an ESD protection structure employing a biasing element connected between two Zener diodes placed in opposition with each other. As can be appreciated, these and other known ESD protection structures involve relatively complicated circuitry.
The ESD-related problems may be particularly exacerbated in portable data carriers, electronic tokens and the like, having a microcircuit inside a housing formed from at least two conductive surfaces. Typically, these devices are interrogated by a read/write unit over a minimum of conductive paths such as, for example, an input/output path and a ground path. Some of these devices may tolerate an ESD stress at the 26 kV level (which corresponds to the International Electrotechnical Commission Standard IEC-801-2) without a hard failure. However, it has been known that in some applications these devices may suffer data disturb failures with an ESD stress below this level.
The present invention, described and claimed hereinbelow, provides a simple yet robust ESD solution for protecting the ICs without the above-mentioned deficiencies and shortcomings.